1. Technical Field
The disclosure relates in general to a display panel and a manufacturing method thereof, and, in particular, to a liquid crystal display (LCD) panel and a manufacturing method thereof.
2. Related Art
The LCD panel is one of increasingly popular display panels and advantageously has high resolution, light weight, thin thickness and low power consumption. However, the current LCD panel still has some technological problems to be solved. For example, the problem of wide view angle exists, in which the user sees the displayed image with the different gray-scale levels and brightness when he or she is watching the image from the front or at an angle from either right or left side of the display. Usually, the brightness of the image viewed by the user from the front of the display is higher than that viewed by the user from either side of the display. Therefore, the frames viewed on the LCD apparatus at different angles have different brightness, which causes different color mixing results. Thus, the phenomena of color shift and color de-saturation tend to occur.
Referring to FIGS. 1 and 2, a sub-pixel structure 1 of a conventional multi-domain vertically aligned (MVA) LCD panel includes at least one TFT (Thin Film Transistor) T, a storage capacitance line 11, a sub-pixel electrode 12, a liquid crystal layer 13 and a common electrode 14. The common electrode 14 is formed on a color filter substrate 16. The sub-pixel electrode 12 is formed on a dielectric layer 17 of a TFT substrate 15. The liquid crystal layer 13 is accommodated between the sub-pixel electrode 12 and the common electrode 14. The sub-pixel electrode 12 is disposed between two neighboring scan lines SLn and SLn+1, and the sub-pixel electrode 12 has a plurality of slits 12a so that the sub-pixel electrode 12 is formed with a pattern. The TFT T controls the operation of the sub-pixel structure 1, and a storage capacitor is formed between the storage capacitance line 11 and the sub-pixel electrode 12.
As mentioned hereinabove, the slits 12a or alignment protrusions 14a are arranged on the TFT substrate 15 or the color filter substrate 16 in the MVA LCD panel so that liquid crystal molecules are arranged in multiple directions and several alignment domains can be obtained to improve the problem of wide view angle.
Recently, another technology has been proposed in order to improve the color shift problem associated with the wide view angle problem more effectively. As shown in FIG. 2, the sub-pixel electrode 12 is divided into a first region I and a second region II in order to display different brightness ratios with respect to different gray-scale levels. In order to achieve this effect, in general, it is possible to turn on a third TFT T3, when the next scan line SLn+1 is being enabled, to conduct charges on an auxiliary capacitor, which is defined by the corresponding arrangement of an extra interconnection 11a of the storage capacitance line 11 and an electrode E having a potential equal to that of a source of the third TFT T3, to the second region II of the sub-pixel electrode 12 so that the brightness difference between the second region II and the first region I is kept constant to prevent the problem of color shift from occurring.
FIG. 3 shows an equivalent circuit diagram of the sub-pixel structure 1. The liquid crystal capacitor Clc(A) is defined by the corresponding arrangement of the first region I (e.g., a bright region) of the sub-pixel electrode 12 and the common electrode 14. The liquid crystal capacitor Clc(B) is defined by the corresponding arrangement of the second region II (e.g., a dark region) of the sub-pixel electrode 12 and the common electrode 14. The storage capacitor Cst(A) is defined by the corresponding arrangement of the storage capacitance line 11 and a capacitor electrode 112, which is electrically connected to the first region of the sub-pixel electrode 12 through a via. The storage capacitor Cst(B) is defined by the corresponding arrangement of the storage capacitance line 11 and a capacitor electrode 111, which is electrically connected to the second region of the sub-pixel electrode 12 through a via. The auxiliary capacitor CS is defined by the corresponding arrangement of the extra interconnection 11a of the storage capacitance line 11 and the electrode E having the potential equal to that of the source of the third TFT T3. The first region I and the second region II of the sub-pixel electrode 12 are respectively disposed corresponding to the common electrode 14, and electrically connected to a data line DLn and the scan line SLn opposite to the data line DLn through a first TFT T1 and a second TFT T2 opposite to the first TFT T1. The second region II of the sub-pixel electrode 12 is electrically connected to the next scan line SLn+1 and the auxiliary capacitor through the corresponding third TFT T3.
FIG. 4 is a schematic time chart showing the operation of the scan lines SLn and SLn+1 as well as nodes VP1 and VP2 in FIG. 3. First, when the scan line SLn inputs a signal to the sub-pixel electrode 12, the first TFT T1 and the second TFT T2 turn on, and sub-pixel data of positive polarity is inputted through the data line DL so that the potentials of the nodes VP1 and VP2 are equal to V1. When the scan line SLn stops inputting the signal to the sub-pixel electrode 12, the first TFT T1 and the second TFT T2 instantaneously turn off. At this time, the nodes VP1 and VP2 encounter different feed-through effects due to the influence the parasitic capacitances between the gates and the drains of the TFTs T1 and T2. Thus, the potentials of the nodes VP1 and VP2 are different from each other and are respectively V2 and V21, and the level difference therebetween relative to a common voltage Vcom is about (V2−V21). Next, when the scan line SLn+1 inputs the signal to the sub-pixel electrode 12, the previous frame is influenced by the dot inversion factor. So, when the third TFT T3 turns on, the charges stored in the storage capacitor Cst(B) neutralize the auxiliary capacitor CS and the voltage level of the node VP2 is changed to V3 while the voltage level of the node VP1 is still V2. When the scan line SLn+1 stops inputting the signal, the potentials of the nodes VP1 and VP2 are respectively kept at V2 and V3. When the next frame time comes, the scan line SLn again inputs the signal to turn on the first TFT T1 and the second TFT T2, and inputs the sub-pixel data of negative polarity through the data line DL so that the potentials of the nodes VP1 and VP2 are simultaneously made equal to V4. When the scan line SLn stops inputting the signal, the first TFT T1 and the second TFT T2 instantaneously turn off, and the potentials of the nodes VP1 and VP2 are influenced by different feed-through effects and are thus respectively equal to V5 and V51. So, the level difference therebetween relative to the common voltage Vcom is about (V5−V51). Next, the scan line SLn+1 inputs the signal to turn on the third TFT T3 so that the charges of the previous frame with the positive polarity stored in the storage capacitor Cst(B) are transferred to the auxiliary capacitor CS, and the voltage level of the node VP2 is changed to V6. Meanwhile, the voltage level of the node VP1 is still equal to V5. When the scan line SLn+1 stops inputting the signal, the potentials of the nodes VP1 and VP2 are respectively equal to V5 and V6.
However, no matter which method is utilized, the storage capacitance line 11 in the sub-pixel structure 1 is disposed at a middle position of the sub-pixel electrode 12. When the extra interconnection 11a has to be additionally formed through the storage capacitance line 11 in order to adjust the capacitance, the difficulty and the loading of interconnection of the storage capacitance line 11 will be increased, and the aperture ratio will be decreased. In addition, when the sub-pixel electrode 12 is divided into the first region (bright region) I and the second region (dark region) II and if the bright region I and the dark region II are influenced by different feed-through effects, the signals displayed by two regions of the sub-pixel structure 1 have different levels relative to the signal center point Vcom. Thus, the signal may have the problem of flickering among different frames, and a retained image caused by the polarization of the liquid crystal molecules cannot disappear after a long period of time.
Therefore, there is a need to provide a LCD panel and a manufacturing method thereof, wherein the difficulty of interconnection can be simplified, the influence of the low gray-scale region on the display property can be decreased, and the phenomenon of color shift can be improved.